{
  "date": "2026-10-10",
  "scope": "AS02MC04 10G TX RTL subchain simulation; not hardware certification",
  "tool": "AMD Vivado XSim 2026.1",
  "status": "PASS",
  "case_count": 22,
  "cases": [
    "PASS chain QD1 MRRS=128 reverse child completion payload",
    "PASS chain QD1 MRRS=256 reverse child completion payload",
    "PASS chain QD1 MRRS=512 reverse child completion payload",
    "PASS chain QD1 MRRS=1024 reverse child completion payload",
    "PASS chain QD1 MRRS=2048 reverse child completion payload",
    "PASS chain QD1 MRRS=4096 reverse child completion payload",
    "PASS chain split 64B completions and reverse children",
    "PASS chain QD8 interleave reverse children",
    "PASS chain QD8 eight pages physical pool pressure random output stalls",
    "PASS chain error=1 unique terminal failure and same-tag retry",
    "PASS chain error=2 unique terminal failure and same-tag retry",
    "PASS chain error=3 unique terminal failure and same-tag retry",
    "PASS chain error=4 unique terminal failure and same-tag retry",
    "PASS chain error=5 unique terminal failure and same-tag retry",
    "PASS chain error=6 unique terminal failure and same-tag retry",
    "PASS chain early error cancels tail stable stalled RQ expired-tag drop retry",
    "PASS chain FLR abort drains accepted physical tags",
    "PASS chain concurrent abort final completion pending descriptor cancellation",
    "PASS chain session closure drains active page",
    "PASS chain nonterminal error keeps tag until garbage terminal timeout dummy",
    "PASS chain QD8 high tag rejected without aliasing legal page",
    "PASS chain unaligned request rejected"
  ],
  "simulation_log_sha256": "7d7992e4f5e5026b2828a228ee6e80325014e024b413b8e95cbcb6f6538dd0c9",
  "source_files": [
    {
      "file": "cx3_dma_read_guard.sv",
      "sha256": "0b69d07f5e1534a1f64dd158b6bc20e47fb7cbb635fa42f7880335332887261a",
      "matches_prior_manifest": false
    },
    {
      "file": "cx3_rc_tag_router.sv",
      "sha256": "a2a0c574625823ebf958b7603eb072f63a7eb54e70063b0865199fbe04dcabe1",
      "matches_prior_manifest": false
    },
    {
      "file": "pcileech_cpl_page_reorder.sv",
      "sha256": "78fb3c970704f0eb71b266c6a40d73b80534a0b31e035f57e3ef76ceac561402",
      "matches_prior_manifest": false
    },
    {
      "file": "pcie_us_if_rc.v",
      "sha256": "77120ee2f1c5fed3fa82fc8965d69535b9fe16ffe4c0e1a9e2fd1bef969d3208",
      "matches_prior_manifest": true
    },
    {
      "file": "fpga_core.sv",
      "sha256": "028bf34f62dfd706793306015642e9184db79a2fc43c04ca90dc54938c034ca1",
      "matches_prior_manifest": false
    },
    {
      "file": "fpga_core.sv",
      "sha256": "028bf34f62dfd706793306015642e9184db79a2fc43c04ca90dc54938c034ca1",
      "matches_prior_manifest": false
    },
    {
      "file": "pcileech_tlp_bridge_us.sv",
      "sha256": "e44f38cc011d1a1b81dc6533473e1a2336c87e5e337a6826b817edc5f0e5e556",
      "matches_prior_manifest": true
    },
    {
      "file": "pcileech_protocol_us.sv",
      "sha256": "40c33c4ebd5b70133eb2d86fa672bb09c2b81babf7801b981f718b2b82ddfdb1",
      "matches_prior_manifest": true
    },
    {
      "file": "pcileech_rawudp_core.sv",
      "sha256": "ee07432df06e6ba1587ccd4ebaa3e78a0fa816e6a729061293e297c6092a0004",
      "matches_prior_manifest": true
    }
  ],
  "limitations": [
    "No physical board, live host memory or throughput test",
    "Not certification of 325T/25G models",
    "Subchain test does not cover full Ethernet end-to-end path or hardware authorization",
    "Compiler port-width warnings and unconnected pre-terminal hint ports remain"
  ]
}